1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology and, more particularly, to an internal voltage generator of a semiconductor device.
2. Description of the Related Art
Generally, semiconductor devices generate an internal voltages required for internal operations based on a power source voltage VDD and a ground voltage VSS supplied from an external source. For example a memory device such as a Dynamic Random Access Memory (DRAM) generates a core voltage VCORE supplied to a memory core region, a boosted voltage VPP used for driving word lines, and a reduced voltage VBB supplied as a back bias voltage of an NMOS transistor in a core region. Hereinafter, an example of a semiconductor device generating a core voltage VCORE is described.
Specifically, FIG. 1 is a block diagram illustrating a conventional internal voltage generator 100 of a semiconductor device.
Referring to FIG. 1, the conventional internal voltage generator 100 may include a comparison block 110 a driving block 120, and a feedback block 130.
The comparison block 110 typically compares a feedback voltage VFDB with a reference voltage VREFC and generates an analog comparison signal VDIF according to the comparison result. The driving block 120 generates a core voltage VCORE in response to the comparison signal VDIF.
The feedback block 130 typically generates the feedback voltage VFDB that has a voltage level corresponding to the core voltage VCORE.
FIG. 2 is a detailed diagram of the internal voltage generator 100 shown in FIG. 1.
Referring to FIG. 2, the comparison block 110 includes a differential amplifier including a first PMOS transistor MXP0 a second PMOS transistor MXP1 a first NMOS transistor MXN0 a second NMOS transistor MXN1, and a third NMOS transistor MXN2. The first PMOS transistor MXP0 has a source coupled to a power source voltage VDD terminal, a drain coupled to a first output terminal DRV and a gate coupled to a second output terminal MIR. The second PMOS transistor MXP1 has a drain and a gate that are coupled to the second output terminal MIR and a source coupled to the power source voltage VDD terminal, The first NMOS transistor MXN0 has a source coupled to a common coupling terminal CC, a drain coupled to the first output terminal DRV and a gate receiving the reference voltage VREFC. The second NMOS transistor MXN1 has a source coupled to the common coupling terminal CC, a drain coupled to the second output terminal MIR and a gate receiving the feedback voltage VFDB. The third NMOS transistor MXN2 has a source coupled to a ground voltage VSS terminal, a drain coupled to the common coupling terminal CC and a gate receiving a bias voltage VBIAS.
The comparison signal VDIF is outputted through the first output terminal DRV. The bias voltage VBIAS is inputted as an enable signal for enabling the comparison block 110.
The driving block 120 typically drives a core voltage VCORE terminal with a power source voltage VDD in response to the comparison signal VINE. For example, the driving block 120 includes a third PMOS transistor MXP2. The third PMOS transistor MXP2 has a source coupled to the power source voltage VDD terminal, a drain coupled to the core voltage VCORE terminal and a gate receiving the comparison signal VDIF.
The feedback block 130 typically divides the core voltage VCORE at a preset division ratio to generate the feedback voltage VFDB. For example, the feedback block 130 includes a fourth NMOS transistor MXN3 and a fifth NMOS transistor MXN4. The fourth NMOS transistor MXN3 has a drain and a gate that are coupled to the core voltage VCORE terminal and a source coupled to a feedback voltage terminal FDB, The fifth NMOS transistor MXN4 has a drain and a gate that are coupled to the feedback voltage terminal FDB and a source coupled to the ground voltage VSS terminal.
A case where the core voltage VCORE is lowered is now described. For example, the core voltage VCORE may be lowered below a target level of the core voltage VCORE when a load current occurs.
The comparison block 110 compares the feedback voltage VFDB with the reference voltage VREFC and generates the comparison signal VDIF corresponding to the comparison result. When the feedback voltage VFDB is lower than the reference voltage VREFC, the comparison block 110 generates the comparison signal VDIF whose voltage level may be lowered to correspond to a voltage difference between the feedback voltage VFDB and the reference voltage VREFC.
For example, when the core voltage VCORE is lowered below the target level of the core voltage VCORE, the feedback voltage VFDB may become lower than the reference voltage VREFC and thus a voltage level of the first output terminal DRV may become lower as well. Therefore, the voltage level of the comparison signal VDIF may be lowered to correspond to the voltage level of the first output terminal DRV.
The driving block 120 turns on and drive the core voltage VCORE terminal with the power source voltage VDD in response to the comparison signal VDIF. Therefore, the core voltage VCORE increases.
A case where the core voltage VCORE is increased is now described. For example, the core voltage VCORE may keep the target level of the core voltage VCORE or increase above the target level of the core voltage VCORE by the driving block 120.
The comparison block 110 typically compares the reference voltage VREFC with the feedback voltage VFDB and generates the comparison signal VDIF corresponding to the comparison result. When the feedback voltage VFDB is higher than the reference voltage VREFC, the comparison block 110 generates the comparison signal VDIF whose voltage level increases corresponding to the voltage difference between the feedback voltage VFDB and the reference voltage VREFC.
For example, when the core voltage VCORE increases above the target level of the core voltage VCORE, the feedback voltage VFDB may also increase above the reference voltage VREFC and thus, the voltage level of the first output terminal DRV may be increased. Therefore, the voltage level of the comparison signal VDIF may be increased corresponding to the voltage level of the first output terminal DRV.
The driving block 120 may be turned off in response to the comparison signal VDIF causing the core voltage VCORE to be lowered.
Hence, a conventional internal voltage generator 100, may maintain the core voltage VCORE at a target level. However, some issues may occur.
For example, the comparison signal VDIF is an analog signal that varies corresponding to the voltage level of the first output terminal DRV. The driving block 120 operates in response to the comparison signal VDIF that is the analog signal. Therefore, in a conventional internal voltage generator 100 a fluctuation of the core voltage VCORE may occur and current consumption increase.
Further, generally, as the internal voltage generator 100 is formed in a regulator type, a response time required for sensing and compensating for the fluctuation of the core voltage VCORE may be slow.